Switched-mode DC-DC converters are commonly used to provide the voltage required for operating electronic circuits from a differing supply voltage with minimal losses. An example of a DC-DC converter (in this case a buck converter, configured to reduce the supply voltage) is depicted in FIG. 1. Although a buck converter is shown in FIG. 1, it is to be understood that the discussion below applies to any converter configuration.
In the configuration shown in FIG. 1, the series switch (hereinafter SW1) and the shunt switch (hereinafter SW2) are alternately closed in order to provide a varying output voltage to the load. Simplified control waveforms for the switches are depicted in FIG. 2. When the series switch SW1 is on, current flows from the input voltage through SW1 to the output inductor Lout. When the series switch SW1 is off, and the shunt switch SW2 is on, the inductor draws current from the ground node through SW2, which acts as a synchronous rectifier. (It is also possible to have the current decrease to 0 or become negative during this portion of the operating cycle.) The duty cycle D is defined as the proportion of time during which SW1 is on:
  D  =            T      on                      T        on            +              T        off            
In normal steady-state continuous-mode operation, when parasitic losses can be neglected, the output voltage is proportional to the duty cycle:Vout=DVin 
If both switches are on simultaneously, current can flow through them directly from the input voltage supply to ground. This “shoot-through” current can be very large, since its only impediment is the on-resistance of the switches. Shoot-through current does not flow through the load and so is wasted, degrading the efficiency of the converter. Therefore, shoot-through is to be avoided. In order to accomplish this end, “dead times” are normally provided at the end of each switch on-time, during which both switches are off.
During the dead times, current continues to flow due to the influence of the typically large-value output inductor Lout. Since both switches are open, this current will charge or discharge the parasitic capacitance of the switch node, which is typically small. As a consequence it is often the case that the potential at the switch node VSW, hereinafter referred to as the switching voltage, will change rapidly during the dead times. In the typical continuous-conduction case where the current through the inductor is positive at all times in the switching cycle, the voltage VSW will fall (become more negative), as depicted in FIG. 3.
During the dead time DT1, at the beginning of which the switch potential is already near 0, VSW becomes negative. If DT1 is too long, the body diode of the switch FET SW2 turns on (or the FET itself will turn on as an MOS diode), and current starts to flow out of the diode into the output inductor. Body diode current degrades converter efficiency, due to dissipation as it flows through the diode of P=IBVF, where VF is the forward voltage of the diode and IB is the body-diode current. The forward voltage of a junction diode is typically about 0.7 V (for MOSFET devices, the diode voltage can be higher or lower than 0.7V, but there is still loss). In application where the output voltage is modest (e.g. 1 to 5 V), this represents a substantial additional loss mechanism. Therefore, when current flow through the output inductor is positive during DT1, it is best to make the dead time DT1 as short as possible consistent with avoiding shoot-through current.
Note that in the case where the instantaneous current flowing through the inductor is negative during DT1, the voltage VSW increases towards VIN during the dead time. The best efficiency is obtained when DT1 is long enough that the node voltage reaches VIN, at which point SW1 is turned on. Since there is no voltage across SW1 when it is turned on, there is no switching loss. This is known as Zero Voltage Switching (ZVS). However, for small negative currents, long dead times are needed, so efficiency benefits must be balanced against duty cycle constraints, as described below.
During the dead time DT2, at the beginning of which the switch potential is near the input potential VIN, VSW falls towards 0, discharging charge stored on the parasitic capacitance of the VSW node into the load. If SW2 is turned on at the moment that VSW reaches 0 V, all the energy stored in SW2 will have flowed to the load, and since there is no voltage across SW2 at the moment of switching, there is no power dissipated during the switching transition (This is ZVS operation for DT2). If DT2 is allowed to become too long, the switch node voltage again becomes negative, and body diode current may flow, increasing dissipation and decreasing efficiency. It is desirable to choose DT2 to approximate ZVS as closely as possible to achieve maximum efficiency, without extending the time excessively so as to avoid body diode current.
The dead times required for efficient operation vary with the node capacitances, output inductance, applied voltage, and output current. In applications where the output current is substantially constant and known a priori, it may be possible to use fixed values for both DT1 and DT2 and achieve good efficiency. However, in applications where the output current experiences wide and frequent variations, dead time adjustments are helpful for maintaining good efficiency. This is of particular import for high-frequency converters using switching frequencies fSW>10 MHz, since the loss associated with switching transitions is linear in the frequency of occurrence of those transitions.
Therefore, it is of interest to adjust the dead times used in converter operation to obtain optimal efficiency, particularly in the case where output voltages comparable to the forward voltage of the body diode are contemplated.
A variety of approaches have been reported to achieve this end. The dead times may be set by design, but in this case variations in device characteristics due to processing variations are not accounted for, and changes in load current cannot be accommodated without degraded efficiency. In order to avoid shoot-through current, dead times must be set excessively long, leading to low efficiency from body-diode conduction. Adjustments may be made in the dead times when the final device or assembly is tested, to correct for process variations, but variations in temperature and operating current are not accounted for, again forcing the adjusted dead times to be set conservatively to avoid shoot-through current, thereby failing to achieve optimal efficiency.
Adaptive gate control may be used, in which the zero-crossing times are sensed directly by gates attached to the switching node and the SW2 control node. Such techniques are suitable for low-frequency converters (with switching frequencies of 100 kHz or less). However, when higher frequencies are used, especially in high-frequency converters using switching frequencies fSW>10 MHz, the delays in the control circuitry are comparable to the switching times, and accurate operation is difficult to achieve.
Predictive control of dead times, in which overlap in one switch cycle is used to adjust the dead time employed in the next switch cycle, has been reported. Predictive and loop control methods correct for the sensitivity of the control procedure to delays in the sensing circuitry, but require that zero crossings be accurately detected, which is again difficult in the case of high-frequency operation.
The use of converter duty cycle D as a surrogate for efficiency has been described. The duty cycle required to produce a given output voltage is minimized when dissipation in the converter is minimized. Dead times DT1 and DT2 may be adjusted while monitoring the resulting changes in the duty cycle, until a minimum in duty cycle D is found. This approach does not require fast sensing of the switching node, but because the derivative of D with respect to the dead times is being measured, it is necessary to wait for the controller to stabilize for each measurement if good accuracy is to be obtained.
The use of duty cycle optimization for dead time control is acceptable when adaptation of the dead times is infrequent and long adaptation periods are allowed. However, in applications where load conditions change frequently and adaptation must proceed quickly, such long calibration times are not acceptable. For example, when a converter is used to supply a power amplifier used in Wideband Code-Division Multiplexed (WCDMA) communications, the transmitted power is modified for each 667-microsecond slot during closed-loop power control. Improved system efficiency is achieved by changing the voltage supplied to the power amplifier each time the requested RF power is changed. Any calibration process must take place in a time much shorter than 667 microseconds to be useful. If twenty steps are required to optimize each dead time, and each step requires 100 switching periods to perform, a conventional 1 MHz converter requires 4 milliseconds to find the optimal dead times, much longer than the slot time. Even if a much higher switching frequency (for example, 20 MHz) is used, 200 microseconds is required to establish optimal values for operation in a 667-microsecond slot, which is relatively wasteful.
Finally, some methods include the use of a memory or lookup table, possibly in combination with dead-time-based calibration, for fast dead time adaptation. This approach provides rapid adaptation if fast memory access is available. However, appropriate sensors are required, at least for the DC output current. While it is straightforward to sense output current using a resistive sensor, efficiency is degraded when a large sense resistance is employed, and noise margins are degraded if a small resistor is used. Various alternatives for current sensing have been reported, but these approaches generally add to power consumption and thus degrade efficiency. Furthermore, in any lookup table approach, a relatively complex periodic calibration is required to guard against variations in temperature and device aging.
It is desirable to have methods and apparatus for setting optimal device times in a switched-mode converter which are fast, adaptable to varying temperatures, voltages, and currents, and suitable for use with high switching frequencies.